As is known in the art, modern semiconductor packages take on various forms, including pin grid arrays (PGAs), ball grid arrays (BGAs), die-scale packages (CSPs), etc. In such types of packages, the semiconductor die may be flip-chip mounted to a substrate, wherein the active surface of the semiconductor die is bumped and bonded to an underlying substrate, and wire-bonded to the substrate, wherein bond pads formed on the active surface of the substrate are connected to conjugate bond pads on a substrate via wire-bonds. The substrates for such types of packages may take on various forms, including ceramic, plastic, and metal having an insulating coating (so called "metal core substrates"). As is known in the art, the substrate includes a plurality of interconnects that electrically interconnect die terminals to respective substrate terminals, the substrate terminals being arranged in an array fashion at a relatively large pitch for electrical connection to a printed circuit board, for example. This type of structure is more clearly shown in connection with FIG. 1, described below.
FIG. 1 depicts a packaged semiconductor device 1 including semiconductor die 10 which is provided on and electrically connected to substrate 20. As is known in the art, the semiconductor die 10 includes a semiconducting substrate, such as doped silicon, on which is formed a plurality (i.e., literally thousands) of transistors. A plurality of dielectric layers and higher-level metal layers are lithographically defined and deposited on the semiconducting substrate so as to form a complete semiconductor die, which is coated with a passivation layer. The particular details of the semiconductor die are known in the art and are not essential for an understanding of the structure shown in FIG. 1. Semiconductor die 10 includes a plurality of die terminals 12 that electrically connect the semiconductor die 10 to the substrate 20. The die terminals 12 are formed to overlie an active surface of the die. The die terminals shown include die pads 14, on which are formed solder bumps 13 by the known Controlled Collapse Chip Connection (C4) technology. The die terminals 12 are electrically connected to substrate pads 21. The die pads 14 include signal pads 14a (also known as I/O pads), power pads 14b, and ground pads 14c, the power and ground pads 14b and 14c collectively forming supply pads.
The die terminals 12 provide electrical and mechanical connection by reflow of the solder material of the solder bumps 13 with a flux so as to provide electrical connection between the semiconductor die 10 and the substrate.
Turning to the substrate 20, a plurality of interconnects 22 are provided to effect electrical connection between the die terminals 12 and substrate terminals 30. The interconnects include signal interconnects 22a, power interconnects 22b, and ground interconnects 22c. The power and ground interconnects 22b and 22c are generically referred to as supply interconnects. Each interconnect 22 includes die-scale vias 24 which are connected to respective printed wires 28, and to respective package-scale vias 26. The die-scale vias 24 are arranged at a pitch corresponding to the pitch of the die terminals 12, which is a relatively fine pitch. The printed wires 28 are provided in respective layers of the substrate, and serve to fan-out electrical connection to package-scale vias 26, which are arranged at a pitch greater than die-scale vias 24. In the structure shown in FIG. 1, the substrate is formed of a plurality of ceramic layers, wherein the printed wires 28 are formed on respective ceramic layers, and vias 24 and 26 are lithographically defined and formed. The printed wires 28 take the form of printed lines when formed as a component of a signal interconnect 22a, but take the form of ground planes and power planes when used in connection with ground interconnects and power interconnects, 22b and 22c, respectively.
Substrate terminals 30 include signal terminals 30a, power terminals 30b, and ground terminals 30c. Power terminals 30b and ground terminals 30c are collectively described as supply terminals. In the structure shown in FIG. 1, the substrate terminals 30 include landing pads 32, having associated solder balls 34 for electrical connection to a printed circuit board.
The present inventor has recognized numerous shortcomings with the prior art semiconductor device depicted in FIG. 1. Particularly, it has been found that the substrate is responsible for a certain degree of switching noise, caused by relatively high mutual loop inductance (L.sub.m) between supply interconnects and signal interconnects. Accordingly, a need exists in the art to provide an improved packaged semiconductor device, particularly, an improved interconnect structure of a substrate of the packaged semiconductor device, for reducing mutual loop inductance (L.sub.m).